Responsibilities:

• Define and implement test plans and verification plans based on specifications and requirements.(10%)

• Develop assertion-based checkers and functional coverage metrics based on verifications plans.(20%)

• Perform functional verification of RTL designs using industry-standard tools and methodologies.(20%)

• Generate and analyze coverage reports to ensure thorough verification.(20%)

• Collaborate with design and architecture teams to understand design specifications and requirements.(10%)

• Identify and resolve verification issues and bugs.(10%)

• Continuously improve verification processes and methodologies.(10%)

Minimum Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

• Minimum 6 years of experience in SOC verification.

• Hands-on verification experience using UVM methodology

• Strong understanding of test and verification plan definition and implementation.

• Experience with coverage-driven verification and coverage report generation.

• Familiarity with industry-standard verification tools (e.g.,VCS, QuestaSim).

• Experience with IC design verification.

• Knowledge of HDL methodology with the most recent experience in UVM.

• Proficiency in SystemVerilog and assertion-based verification.

• Experience with formal verification.

• Hands-on verification experience of Bus Fabric, NOC, AMBA-AHB/AXI based bus architecture in a UVM environment.

• Knowledge of Low Power Verification

• Excellent problem-solving skills and attention to detail.

• Strong communication and teamwork skills.

Desired Qualifications

• Strong knowledge in Python programming

• Experience in wireless SoC design and verification.

• Knowledge of scripting languages (e.g., TCL, Python, Perl) for automation.

• Familiarity with version control systems (e.g., Git).